Semiconductor devices may be divided into various categories, including memory devices and non-memory devices. In memory devices, information may be stored, and in non-memory devices, information may not be stored.
Memory devices may be generally divided into volatile memory devices, in which recorded information may be erased and new information may be stored, and non-volatile memory devices, in which information recorded once may be permanently stored.
Volatile memory devices may include RAM (Random Access Memory), which may allow information to be written and read. Non-volatile memory may include ROM (Read Only Memory), EPROM (Erasable Programmable ROM), and EEPROM (Electrically Erasable Programmable ROM), which may allow information to be read.
Memory and non-memory devices may be simultaneously designed in accordance with a various known layouts on a semiconductor substrate.
FIG. 1 is an example sectional diagram showing a semiconductor device having memory and non-memory devices.
Referring to FIG. 1, memory and non-memory devices 1 and 2 may be formed on a semiconductor substrate 3.
Memory device 1 may include gate insulating layer 6a, floating gate 7, interlayer dielectric layer 8, and control gate 9. These elements may be stacked. Source and drain areas 4a and 4b may be formed at both side areas of control gate 9.
Interlayer dielectric layer 8 may be an ONO (Oxide-Nitride-Oxide) layer. Floating gate 7 may be an area in which information is written. Gate insulating layer 6a may be formed to isolate semiconductor substrate 3 and floating gate 7. Control gate 9 may be formed to control floating gate 7, for example to write or delete information. Interlayer dielectric layer 8 may be formed to isolate floating gate 7 and control gate 9.
Spacer 10a may be formed at sides of gate insulating layer 6a, floating gate 7, interlayer dielectric layer 8 and control gate 9.
In non-memory device 2, gate insulating layer 6b and general gate 9a may be stacked. Source and drain areas 5a and 5b may be formed at both side areas of general gate 9a. General gate 9a may conduct and cut off a channel area between source and drain areas 5a and 5b such that signals may be transmitted therebetween.
Further, gate insulating layer 6b may be formed to isolate semiconductor substrate 3 and general gate 9a. Spacer 10b may be formed at sides of gate insulating layer 6b and general gate 9a. 
PMD (Pre-Metallic Dielectric) layer 12 may be formed on semiconductor substrate 3. PMD layer 12 may include contact holes for electrical connections to general gate 9a, control gate 9, source areas 4a and 5a, and drain areas 4b and 5b. Metal interconnection 13 may be formed through each of the contact holes, and tungsten (W) 11 may be filled in the contact hole.
Control gate 9 may include a material substantially identical to a material forming general gate 9a. 
Therefore, control gate 9 and general gate 9a may be formed through a one-time mask process in a semiconductor process.
However, since a step difference may exist between control gate 9 and general gate 9a, focuses for exposure may be different from each other when performing an exposure process, for example to form a photoresist pattern. For this reason, it may not be possible to simultaneously form control gate 9 and general gate 9a through a one-time mask process.
For example, since control gate 9 may be formed on floating gate 7 and interlayer dielectric layer 8, control gate 9 may be positioned higher than general gate 9a by a height of floating gate 7 and interlayer dielectric layer 8.
Accordingly, a step difference may be formed as high as floating gate 7 and interlayer dielectric layer 8 between control gate 9 and general gate 9a. 
Thus, if a focus for exposure is adjusted on a photoresist on interlayer dielectric layer 8 to deposit the photoresist on semiconductor substrate 3 including interlayer dielectric layer 8 and then expose the photoresist, the focus may not be properly adjusted on the photoresist in an area in which general gate 9a will be formed.
If an exposure is then performed, an exact photoresist pattern may be formed on interlayer dielectric layer 8, while the precise photoresist pattern may not formed on an area in which general gate 9a will be formed.
Thus, since a general gate having an inexact CD (Critical Dimension) may be formed where patterning is performed using an inexact photoresist as a mask, an inexact operation may be accomplished by such a general gate.
Therefore, it may be necessary for a control gate and a general gate, which may have the same material, to be formed through a two-time mask process and not through a one-time mask process. Such a process may be complicated, expensive, and time consuming.